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2024 | OriginalPaper | Chapter

Static Analysis of Current Limited Memristors: A Novel Approach to Investigate Memristor Programming Techniques

Authors : Tommaso Addabbo, Ada Fort, Riccardo Moretti, Valerio Vignoli

Published in: Proceedings of SIE 2023

Publisher: Springer Nature Switzerland

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Abstract

We discuss a novel investigation approach to study the current-limited memristors dynamics for programming purposes. In detail, referring to the case of the Stanford memristor model, we propose to analyze its programming dynamics adopting a nonlinear static analysis point of view, considering different current limiting circuit topologies.

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Literature
2.
go back to reference Kim, T.H., et al.: Multilevel switching memristor by compliance current adjustment for off-chip training of neuromorphic system. Chaos, Solitons Fractals 153, 111587 (2021)CrossRef Kim, T.H., et al.: Multilevel switching memristor by compliance current adjustment for off-chip training of neuromorphic system. Chaos, Solitons Fractals 153, 111587 (2021)CrossRef
3.
go back to reference Zhu, D., et al.: A new operation scheme to obtain 3-bit capacity per cell in HfO\(_2\) based RRAM with high uniformity. In: 2017 Silicon Nanoelectronics Workshop (SNW), pp. 83–84. IEEE (2017) Zhu, D., et al.: A new operation scheme to obtain 3-bit capacity per cell in HfO\(_2\) based RRAM with high uniformity. In: 2017 Silicon Nanoelectronics Workshop (SNW), pp. 83–84. IEEE (2017)
4.
go back to reference Sarkar, P., Bhattacharjee, S., Barman, A., Kanjilal, A., Roy, A.: Multilevel programming in Cu/NiO\(_y\)/NiO\(_x\)/Pt unipolar resistive switching devices. Nanotechnology 27(43), 435701 (2016)CrossRef Sarkar, P., Bhattacharjee, S., Barman, A., Kanjilal, A., Roy, A.: Multilevel programming in Cu/NiO\(_y\)/NiO\(_x\)/Pt unipolar resistive switching devices. Nanotechnology 27(43), 435701 (2016)CrossRef
5.
go back to reference Bousoulas, P., Stathopoulos, S., Tsialoukis, D., Tsoukalas, D.: Low-power and highly uniform 3-b multilevel switching in forming free TiO\(_{2-x}\)-based RRAM with embedded Pt nanocrystals. IEEE Electron Device Lett. 37(7), 874–877 (2016)CrossRef Bousoulas, P., Stathopoulos, S., Tsialoukis, D., Tsoukalas, D.: Low-power and highly uniform 3-b multilevel switching in forming free TiO\(_{2-x}\)-based RRAM with embedded Pt nanocrystals. IEEE Electron Device Lett. 37(7), 874–877 (2016)CrossRef
6.
go back to reference Hardtdegen, A., et al.: Internal cell resistance as the origin of abrupt reset behavior in HfO\(_2\)-based devices determined from current compliance series. In: 2016 IEEE 8th International Memory Workshop (IMW), pp. 1–4. IEEE (2016) Hardtdegen, A., et al.: Internal cell resistance as the origin of abrupt reset behavior in HfO\(_2\)-based devices determined from current compliance series. In: 2016 IEEE 8th International Memory Workshop (IMW), pp. 1–4. IEEE (2016)
7.
go back to reference Xu, X., et al.: Degradation of gate voltage controlled multilevel storage in one transistor one resistor electrochemical metallization cell. IEEE Electron Device Lett. 36(6), 555–557 (2015)CrossRef Xu, X., et al.: Degradation of gate voltage controlled multilevel storage in one transistor one resistor electrochemical metallization cell. IEEE Electron Device Lett. 36(6), 555–557 (2015)CrossRef
8.
go back to reference Misha, S.H., et al.: Effect of nitrogen doping on variability of TaO\(_x\)-RRAM for low-power 3-bit MLC applications. ECS Solid State Lett. 4(3), P25 (2015)CrossRef Misha, S.H., et al.: Effect of nitrogen doping on variability of TaO\(_x\)-RRAM for low-power 3-bit MLC applications. ECS Solid State Lett. 4(3), P25 (2015)CrossRef
9.
go back to reference Prakash, A., Park, J., Song, J., Woo, J., Cha, E.J., Hwang, H.: Demonstration of low power 3-bit multilevel cell characteristics in a TaO\(_x\)-based RRAM by stack engineering. IEEE Electron Device Lett. 36(1), 32–34 (2014)CrossRef Prakash, A., Park, J., Song, J., Woo, J., Cha, E.J., Hwang, H.: Demonstration of low power 3-bit multilevel cell characteristics in a TaO\(_x\)-based RRAM by stack engineering. IEEE Electron Device Lett. 36(1), 32–34 (2014)CrossRef
10.
go back to reference Long, B., Li, Y., Jha, R.: Switching characteristics of Ru/HfO\(_2\)/TiO\(_{2-x}\)/Ru RRAM devices for digital and analog nonvolatile memory applications. IEEE Electron Device Lett. 33(5), 706–708 (2012)CrossRef Long, B., Li, Y., Jha, R.: Switching characteristics of Ru/HfO\(_2\)/TiO\(_{2-x}\)/Ru RRAM devices for digital and analog nonvolatile memory applications. IEEE Electron Device Lett. 33(5), 706–708 (2012)CrossRef
11.
go back to reference Chen, Y.X., Li, J.F.: Fault modeling and testing of 1T1R memristor memories. In: 2015 IEEE 33rd VLSI Test Symposium (VTS), pp. 1–6. IEEE (2015) Chen, Y.X., Li, J.F.: Fault modeling and testing of 1T1R memristor memories. In: 2015 IEEE 33rd VLSI Test Symposium (VTS), pp. 1–6. IEEE (2015)
12.
go back to reference Wang, Z., et al.: Reinforcement learning with analogue memristor arrays. Nat. Electron. 2(3), 115–124 (2019)CrossRef Wang, Z., et al.: Reinforcement learning with analogue memristor arrays. Nat. Electron. 2(3), 115–124 (2019)CrossRef
13.
go back to reference Merced-Grafals, E.J., Dávila, N., Ge, N., Williams, R.S., Strachan, J.P.: Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications. Nanotechnology 27(36), 365202 (2016)CrossRef Merced-Grafals, E.J., Dávila, N., Ge, N., Williams, R.S., Strachan, J.P.: Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications. Nanotechnology 27(36), 365202 (2016)CrossRef
14.
go back to reference Addabbo, T., Moretti, R.: Static analysis of current limiting techniques for accurate memristor programming. In: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5. IEEE (2023) Addabbo, T., Moretti, R.: Static analysis of current limiting techniques for accurate memristor programming. In: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5. IEEE (2023)
15.
go back to reference Chen, P.Y., Yu, S.: Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design. IEEE Trans. Electron Devices 62(12), 4022–4028 (2015)MathSciNetCrossRef Chen, P.Y., Yu, S.: Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design. IEEE Trans. Electron Devices 62(12), 4022–4028 (2015)MathSciNetCrossRef
16.
go back to reference Sheridan, P., Kim, K.H., Gaba, S., Chang, T., Chen, L., Lu, W.: Device and SPICE modeling of RRAM devices. Nanoscale 3(9), 3833–3840 (2011)CrossRef Sheridan, P., Kim, K.H., Gaba, S., Chang, T., Chen, L., Lu, W.: Device and SPICE modeling of RRAM devices. Nanoscale 3(9), 3833–3840 (2011)CrossRef
17.
go back to reference Guan, X., Yu, S., Wong, H.S.P.: A SPICE compact model of metal oxide resistive switching memory with variations. IEEE Electron Device Lett. 33(10), 1405–1407 (2012)CrossRef Guan, X., Yu, S., Wong, H.S.P.: A SPICE compact model of metal oxide resistive switching memory with variations. IEEE Electron Device Lett. 33(10), 1405–1407 (2012)CrossRef
18.
go back to reference Jiang, Z., Yu, S., Wu, Y., Engel, J.H., Guan, X., Wong, H.S.P.: Verilog-A compact model for oxide-based resistive random access memory (RRAM). In: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 41–44. IEEE (2014) Jiang, Z., Yu, S., Wu, Y., Engel, J.H., Guan, X., Wong, H.S.P.: Verilog-A compact model for oxide-based resistive random access memory (RRAM). In: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 41–44. IEEE (2014)
Metadata
Title
Static Analysis of Current Limited Memristors: A Novel Approach to Investigate Memristor Programming Techniques
Authors
Tommaso Addabbo
Ada Fort
Riccardo Moretti
Valerio Vignoli
Copyright Year
2024
DOI
https://doi.org/10.1007/978-3-031-48711-8_41