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22.01.2024

Machine Learning-Based Security Evaluation and Overhead Analysis of Logic Locking

verfasst von: Yeganeh Aghamohammadi, Amin Rezaei

Erschienen in: Journal of Hardware and Systems Security

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Abstract

Piracy and overproduction of hardware intellectual properties are growing concerns for the semiconductor industry under the fabless paradigm. Although chip designers have attempted to secure their designs against these threats by means of logic locking and obfuscation, due to the increasing number of powerful oracle-guided attacks, they are facing an ever-increasing challenge in evaluating the security of their designs and their associated overhead. Especially while many so-called “provable” logic locking techniques are subjected to a novel attack surface, overcoming these attacks may impose a huge overhead on the circuit. Thus, in this paper, after investigating the shortcomings of state-of-the-art graph neural network models in logic locking and refuting the use of hamming distance as a proper key accuracy metric, we employ two machine learning models, a decision tree to predict the security degree of the locked benchmarks and a convolutional neural network to assign a low-overhead and secure locking scheme to a given circuit. We first build multi-label datasets by running different attacks on locked benchmarks with existing logic locking methods to evaluate the security and compute the imposed area overhead. Then, we design and train a decision tree model to learn the features of the created dataset and predict the security degree of each given locked circuit. Furthermore, we utilize a convolutional neural network model to extract more features, obtain higher accuracy, and consider overhead. Then, we put our trained models to the test against different unseen benchmarks. The experimental results reveal that the convolutional neural network model has a higher capability for extracting features from unseen, large datasets which comes in handy in assigning secure and low-overhead logic locking to a given netlist.
Literatur
1.
Zurück zum Zitat Roy JA,Koushanfar F, Markov IL (2008) Epic: Ending piracy of integrated circuits. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1069-1074 Roy JA,Koushanfar F, Markov IL (2008) Epic: Ending piracy of integrated circuits. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1069-1074
2.
Zurück zum Zitat Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2013) Fault analysis-based logic encryption. In: IEEE Transactions on Computers, pp 410-424 Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2013) Fault analysis-based logic encryption. In: IEEE Transactions on Computers, pp 410-424
3.
Zurück zum Zitat Dupuis S, Ba PS, Natale GD, Flottes ML, Rouzeyre B (2014) A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In: International On-Line Testing Symposium (IOLTS), pp 49-54 Dupuis S, Ba PS, Natale GD, Flottes ML, Rouzeyre B (2014) A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In: International On-Line Testing Symposium (IOLTS), pp 49-54
4.
Zurück zum Zitat Baumgarten A, Tyagi A, Zambreno J (2010) Preventing IC piracy using reconfigurable logic barriers. In: IEEE design & Test of computers, pp 66-75 Baumgarten A, Tyagi A, Zambreno J (2010) Preventing IC piracy using reconfigurable logic barriers. In: IEEE design & Test of computers, pp 66-75
5.
Zurück zum Zitat Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic locking algorithms In International Symposium on Hardware Oriented Security and Trust (HOST), pp 137-143 Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic locking algorithms In International Symposium on Hardware Oriented Security and Trust (HOST), pp 137-143
6.
Zurück zum Zitat Shamsi K, Li M, Meade T, Zhao Z, Pan DZ, Jin Y (2017) AppSAT: approximately deobfuscating integrated circuits. In: International Symposium on Hardware Oriented Security and Trust (HOST), pp 95-100 Shamsi K, Li M, Meade T, Zhao Z, Pan DZ, Jin Y (2017) AppSAT: approximately deobfuscating integrated circuits. In: International Symposium on Hardware Oriented Security and Trust (HOST), pp 95-100
7.
Zurück zum Zitat Shen Y, Zhou H (2017) Double DIP: re-evaluating security of logic encryption algorithms. In: Great Lakes Symposium on VLSI (GLSVLSI), pp 179-184 Shen Y, Zhou H (2017) Double DIP: re-evaluating security of logic encryption algorithms. In: Great Lakes Symposium on VLSI (GLSVLSI), pp 179-184
8.
Zurück zum Zitat Rezaei A, Shen Y, Zhou H (2020) Rescuing logic encryption in post-SAT era by locking & obfuscation. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 13-18 Rezaei A, Shen Y, Zhou H (2020) Rescuing logic encryption in post-SAT era by locking & obfuscation. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 13-18
9.
Zurück zum Zitat Plaza SM, Markov IL (2015) Solving the third-shift problem in IC piracy with test-aware logic locking. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 961-971 Plaza SM, Markov IL (2015) Solving the third-shift problem in IC piracy with test-aware logic locking. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 961-971
10.
Zurück zum Zitat Rezaei A, Afsharmazayejani R, Maynard J (2022) Evaluating the security of eFPGA-based redaction algorithms. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 154:1-7 Rezaei A, Afsharmazayejani R, Maynard J (2022) Evaluating the security of eFPGA-based redaction algorithms. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 154:1-7
11.
Zurück zum Zitat Zhou H, Jiang R, Kong S (2017) CycSAT: SAT-based attack on cyclic logic encryptions. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 49-56 Zhou H, Jiang R, Kong S (2017) CycSAT: SAT-based attack on cyclic logic encryptions. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 49-56
12.
Zurück zum Zitat Shen Y, Li Y, Rezaei A, Kong S, Dlott D, Zhou H (2019) BeSAT: behavioral SAT-based attack on cyclic logic encryption. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp 657-662 Shen Y, Li Y, Rezaei A, Kong S, Dlott D, Zhou H (2019) BeSAT: behavioral SAT-based attack on cyclic logic encryption. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp 657-662
13.
Zurück zum Zitat Shen Y, Li Y, Kong S, Rezaei A, Zhou H (2019) SigAttack: new high-level SAT-based attack on logic encryptions. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 940-943 Shen Y, Li Y, Kong S, Rezaei A, Zhou H (2019) SigAttack: new high-level SAT-based attack on logic encryptions. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 940-943
14.
Zurück zum Zitat Shamsi K, Pan DZ, Jin Y (2019) IcySAT: improved SAT-based attacks on cyclic locked circuits. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 1-7 Shamsi K, Pan DZ, Jin Y (2019) IcySAT: improved SAT-based attacks on cyclic locked circuits. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 1-7
15.
Zurück zum Zitat McDaniel I, Zuzak M, Srivastava A (2022) A black-box sensitization attack on SAT-hard instances in logic obfuscation. In: IEEE International Conference on Computer Design (ICCD), pp 239-246 McDaniel I, Zuzak M, Srivastava A (2022) A black-box sensitization attack on SAT-hard instances in logic obfuscation. In: IEEE International Conference on Computer Design (ICCD), pp 239-246
16.
Zurück zum Zitat Yasin M, Mazumdar B, Rajendran J, Sinanoglu O (2016) SARLock: SAT attack resistant logic locking. In: International Symposium on Hardware Oriented Security and Trust (HOST), pp 236-241 Yasin M, Mazumdar B, Rajendran J, Sinanoglu O (2016) SARLock: SAT attack resistant logic locking. In: International Symposium on Hardware Oriented Security and Trust (HOST), pp 236-241
17.
Zurück zum Zitat Xie Y, Srivastava A (2019) Anti-SAT: mitigating SAT attack on logic locking. IEEE Trans Comput-Aided Des Integr Circuits Syst 38(2):199–207CrossRef Xie Y, Srivastava A (2019) Anti-SAT: mitigating SAT attack on logic locking. IEEE Trans Comput-Aided Des Integr Circuits Syst 38(2):199–207CrossRef
18.
Zurück zum Zitat Yasin M, Sengupta A, Nabeel MT, Ashraf M, Rajendran J, Sinanoglu O (2017) Provably-secure logic locking: from theory to practice. In: ACM SIGSAC Conference on Computer and Communications Security (CCS), pp 1601-1618 Yasin M, Sengupta A, Nabeel MT, Ashraf M, Rajendran J, Sinanoglu O (2017) Provably-secure logic locking: from theory to practice. In: ACM SIGSAC Conference on Computer and Communications Security (CCS), pp 1601-1618
19.
Zurück zum Zitat Shamsi K, Meade T, Li M, Pan DZ, Jin Y (2019) On the approximation resiliency of logic locking and IC camouflaging schemes. IEEE Trans Inf Forensics Secur 14(2):347–359CrossRef Shamsi K, Meade T, Li M, Pan DZ, Jin Y (2019) On the approximation resiliency of logic locking and IC camouflaging schemes. IEEE Trans Inf Forensics Secur 14(2):347–359CrossRef
20.
Zurück zum Zitat Shamsi K, Li M, Meade T, Zhao Z, Pan DZ, Jin Y (2017) Cyclic obfuscation for creating SAT-unresolvable circuits. In: Proceedings of the on Great Lakes Symposium on VLSI, pp 173-178 Shamsi K, Li M, Meade T, Zhao Z, Pan DZ, Jin Y (2017) Cyclic obfuscation for creating SAT-unresolvable circuits. In: Proceedings of the on Great Lakes Symposium on VLSI, pp 173-178
21.
Zurück zum Zitat Rezaei A, Shen Y, Kong S, Gu J, Zhou H (2018) Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 85-90 Rezaei A, Shen Y, Kong S, Gu J, Zhou H (2018) Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 85-90
22.
Zurück zum Zitat Rezaei A, Li Y, Shen Y, Kong S, Zhou H (2019) CycSAT-unresolvable cyclic logic encryption using unreachable states. In: Asia and South Pacific Design Automation Conference (ASP-DAC), pp 358-363 Rezaei A, Li Y, Shen Y, Kong S, Zhou H (2019) CycSAT-unresolvable cyclic logic encryption using unreachable states. In: Asia and South Pacific Design Automation Conference (ASP-DAC), pp 358-363
23.
Zurück zum Zitat Rezaei A, Zhou H (2021) Sequential logic encryption against model checking attack. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1178-1181 Rezaei A, Zhou H (2021) Sequential logic encryption against model checking attack. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1178-1181
24.
Zurück zum Zitat Hu B, Tian J, Shihab M, Reddy G, Swartz W, Makris Y, Schaefer BC, Sechen C (2019) Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded FPGA. In: Great Lakes Symposium on VLSI (GLSVLSI), pp 171-176 Hu B, Tian J, Shihab M, Reddy G, Swartz W, Makris Y, Schaefer BC, Sechen C (2019) Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded FPGA. In: Great Lakes Symposium on VLSI (GLSVLSI), pp 171-176
25.
Zurück zum Zitat Mohan P, Atli O, Sweeney J, Kibar O, Pileggi L, Mai K (2021) Hardware redaction via designer-directed fine-grained eFPGA insertion. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1186-1191 Mohan P, Atli O, Sweeney J, Kibar O, Pileggi L, Mai K (2021) Hardware redaction via designer-directed fine-grained eFPGA insertion. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1186-1191
26.
Zurück zum Zitat Bhandari J, Moosa A, Tan B, Pilato C, Gore G, Tang X, Temple S, Gaillardon P, Karri R (2021) Exploring eFPGA-based redaction for IP protection. In: International Conference On Computer Aided Design (ICCAD), pp 1-9 Bhandari J, Moosa A, Tan B, Pilato C, Gore G, Tang X, Temple S, Gaillardon P, Karri R (2021) Exploring eFPGA-based redaction for IP protection. In: International Conference On Computer Aided Design (ICCAD), pp 1-9
27.
Zurück zum Zitat Roshanisefat S, Kamali HM, Homayoun H, Sasan A (2020) SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 954-967 Roshanisefat S, Kamali HM, Homayoun H, Sasan A (2020) SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 954-967
28.
Zurück zum Zitat Kamali HM, Azar KZ, Gaj K, Homayoun H, Sasan A (2018) LUT-Lock: a novel LUT-based logic obfuscation for FPGA bitstream and ASIC-hardware protection. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 405-410 Kamali HM, Azar KZ, Gaj K, Homayoun H, Sasan A (2018) LUT-Lock: a novel LUT-based logic obfuscation for FPGA bitstream and ASIC-hardware protection. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 405-410
29.
Zurück zum Zitat Zhang D, He M, Wang X, Tehranipoor M (2017) Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain. In: VLSI Test Symposium (VTS), pp 1-6 Zhang D, He M, Wang X, Tehranipoor M (2017) Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain. In: VLSI Test Symposium (VTS), pp 1-6
30.
Zurück zum Zitat Karmakar R, Kumar H, Chattopadhyay S (2019) Efficient key gate placement and dynamic scan obfuscation towards robust logic encryption. In: IEEE Transactions on Emerging Topics in Computing Karmakar R, Kumar H, Chattopadhyay S (2019) Efficient key gate placement and dynamic scan obfuscation towards robust logic encryption. In: IEEE Transactions on Emerging Topics in Computing
31.
Zurück zum Zitat Zhou H, Rezaei A, Shen Y (2019) Resolving the trilemma in Logic encryption. In: IEEE International Conference on Computer Aided Design (ICCAD), pp 1-8 Zhou H, Rezaei A, Shen Y (2019) Resolving the trilemma in Logic encryption. In: IEEE International Conference on Computer Aided Design (ICCAD), pp 1-8
32.
Zurück zum Zitat Afsharmazayejani R, Sayadi H, Rezaei A (2022) Distributed logic encryption: essential security requirements and low-overhead implementation. In: Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 127-131 Afsharmazayejani R, Sayadi H, Rezaei A (2022) Distributed logic encryption: essential security requirements and low-overhead implementation. In: Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 127-131
33.
Zurück zum Zitat Rezaei A, Hedayatipour A, Sayadi H, Aliasgari M, Zhou H (2022) Global attack and remedy on IC-specific logic encryption. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 145-148 Rezaei A, Hedayatipour A, Sayadi H, Aliasgari M, Zhou H (2022) Global attack and remedy on IC-specific logic encryption. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 145-148
34.
Zurück zum Zitat Zhang Y, Hu Y, Nuzzo P, Beerel PA (2022) “TriLock: IC protection with tunable corruptibility and resilience to SAT and removal attacks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1329-1334 Zhang Y, Hu Y, Nuzzo P, Beerel PA (2022) “TriLock: IC protection with tunable corruptibility and resilience to SAT and removal attacks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1329-1334
35.
Zurück zum Zitat Maynard J, Rezaei A (2023) DK lock: dual key logic locking against oracle-guided attacks. In: International Symposium on Quality Electronic Design (ISQED), pp. 1-7 Maynard J, Rezaei A (2023) DK lock: dual key logic locking against oracle-guided attacks. In: International Symposium on Quality Electronic Design (ISQED), pp. 1-7
36.
Zurück zum Zitat Sisejkovic D, Reimann LM, Moussavi E, Merchant F, Leupers R (2021) Logic locking at the frontiers of machine learning: a survey on developments and opportunities. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6 Sisejkovic D, Reimann LM, Moussavi E, Merchant F, Leupers R (2021) Logic locking at the frontiers of machine learning: a survey on developments and opportunities. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6
37.
Zurück zum Zitat Chakraborty P, Cruz J, Bhunia S (2018) SAIL: machine learning guided structural analysis attack on hardware obfuscation. In: Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 56-61 Chakraborty P, Cruz J, Bhunia S (2018) SAIL: machine learning guided structural analysis attack on hardware obfuscation. In: Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 56-61
38.
Zurück zum Zitat Chen H, Fu C, Zhao J, Koushanfar F (2019) GenUnlock: an automated genetic algorithm framework for unlocking logic encryption. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-8 Chen H, Fu C, Zhao J, Koushanfar F (2019) GenUnlock: an automated genetic algorithm framework for unlocking logic encryption. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-8
39.
Zurück zum Zitat Alrahis L, Patnaik S, Hanif MA, Saleh H, Shafique M, Sinanoglu O (2021) GNNUnlock+: a systematic methodology for designing graph neural networks-based oracle-less unlocking schemes for provably secure logic locking. IEEE Trans Emerg Topics Comput 10(3):1575-1592 Alrahis L, Patnaik S, Hanif MA, Saleh H, Shafique M, Sinanoglu O (2021) GNNUnlock+: a systematic methodology for designing graph neural networks-based oracle-less unlocking schemes for provably secure logic locking. IEEE Trans Emerg Topics Comput 10(3):1575-1592
40.
Zurück zum Zitat Chen H, Fu C, Zhao J, Koushanfar F (2022) GALU: a genetic algorithm framework for logic unlocking. Research and Practice, In Digital Threats Chen H, Fu C, Zhao J, Koushanfar F (2022) GALU: a genetic algorithm framework for logic unlocking. Research and Practice, In Digital Threats
41.
Zurück zum Zitat Azar KZ, Kamali HM, Homayoun H, Sasan A (2020) NNgSAT: neural network guided SAT attack on logic locked complex structures. In: IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp 1-9 Azar KZ, Kamali HM, Homayoun H, Sasan A (2020) NNgSAT: neural network guided SAT attack on logic locked complex structures. In: IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp 1-9
42.
Zurück zum Zitat Shamsi K, Zhao G (2022) An oracle-less machine-learning attack against lookup-table-based logic locking. In: Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 133-137 Shamsi K, Zhao G (2022) An oracle-less machine-learning attack against lookup-table-based logic locking. In: Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 133-137
43.
Zurück zum Zitat Alrahis L, Patnaik S, Hanif MA, Shafique M, Sinanoglu O (2021) UNTANGLE: unlocking routing and logic obfuscation using graph neural networks-based link prediction. In: IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1-9 Alrahis L, Patnaik S, Hanif MA, Shafique M, Sinanoglu O (2021) UNTANGLE: unlocking routing and logic obfuscation using graph neural networks-based link prediction. In: IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1-9
44.
Zurück zum Zitat Alrahis L, Patnaik S, Shafique M, Sinanoglu O (2021) OMLA: an oracle-less machine learning-based attack on logic locking. IEEE Trans Circuits Syst II Express Briefs 69(3):1602–1606 Alrahis L, Patnaik S, Shafique M, Sinanoglu O (2021) OMLA: an oracle-less machine learning-based attack on logic locking. IEEE Trans Circuits Syst II Express Briefs 69(3):1602–1606
45.
Zurück zum Zitat Sisejkovic D, Merchant F, Reimann LM, Srivastava H, Hallawa A, Leupers R (2021) Challenging the security of logic locking schemes in the era of deep learning: a neuroevolutionary approach. J Emerg Technol Comput Syst 17(3):30 Sisejkovic D, Merchant F, Reimann LM, Srivastava H, Hallawa A, Leupers R (2021) Challenging the security of logic locking schemes in the era of deep learning: a neuroevolutionary approach. J Emerg Technol Comput Syst 17(3):30
46.
Zurück zum Zitat Arp D, Quiring E, Pendlebury F, Warnecke A, Pierazzi F, Wressnegger C, Cavallaro L, Rieck K (2022) Dos and don’ts of machine learning in computer security. In: Proceedings of USENIX Security Symposium Arp D, Quiring E, Pendlebury F, Warnecke A, Pierazzi F, Wressnegger C, Cavallaro L, Rieck K (2022) Dos and don’ts of machine learning in computer security. In: Proceedings of USENIX Security Symposium
47.
Zurück zum Zitat Pilato C, Chowdhury AB, Sciuto D, Garg S, Karri R (2021) ASSURE: RTL locking against an untrusted foundry. IEEE Trans Very Large Scale Integr (VLSI) Syst 29(7):1306-1318 Pilato C, Chowdhury AB, Sciuto D, Garg S, Karri R (2021) ASSURE: RTL locking against an untrusted foundry. IEEE Trans Very Large Scale Integr (VLSI) Syst 29(7):1306-1318
48.
Zurück zum Zitat Alrahis L, Patnaik S, Knechtel J, Saleh H, Mohammad B, Al-Qutayri M, Sinanoglu O (2021) UNSAIL: thwarting oracle-less machine learning attacks on logic locking. IEEE Trans Inf Forensics Secur 16:2508–2523CrossRef Alrahis L, Patnaik S, Knechtel J, Saleh H, Mohammad B, Al-Qutayri M, Sinanoglu O (2021) UNSAIL: thwarting oracle-less machine learning attacks on logic locking. IEEE Trans Inf Forensics Secur 16:2508–2523CrossRef
49.
Zurück zum Zitat Becker GT, Regazzoni F, Paar C, Burleson WP (2013) Stealthy dopant-level hardware Trojans. In: International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp 197-214 Becker GT, Regazzoni F, Paar C, Burleson WP (2013) Stealthy dopant-level hardware Trojans. In: International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp 197-214
50.
Zurück zum Zitat Alasad Q, Yuan J (2017) Logic obfuscation against IC reverse engineering attacks using PLGs. In: IEEE International Conference on Computer Design (ICCD), pp 341-344 Alasad Q, Yuan J (2017) Logic obfuscation against IC reverse engineering attacks using PLGs. In: IEEE International Conference on Computer Design (ICCD), pp 341-344
51.
Zurück zum Zitat Rezaei A, Gu J, Zhou H (2019) Hybrid memristor-CMOS obfuscation against untrusted foundries. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 535-540 Rezaei A, Gu J, Zhou H (2019) Hybrid memristor-CMOS obfuscation against untrusted foundries. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 535-540
52.
Zurück zum Zitat Limaye N, Patnaik S, Sinanoglu O (2022) Valkyrie: vulnerability assessment tool and attack for provably-secure logic locking techniques. IEEE Trans Inf Forensics Secur 17:744–759CrossRef Limaye N, Patnaik S, Sinanoglu O (2022) Valkyrie: vulnerability assessment tool and attack for provably-secure logic locking techniques. IEEE Trans Inf Forensics Secur 17:744–759CrossRef
53.
Zurück zum Zitat Elnaggar R, Chakrabarty K (2018) Machine learning for hardware security: opportunities and risks. In: Journal of Electronic Testing, pp 183-201 Elnaggar R, Chakrabarty K (2018) Machine learning for hardware security: opportunities and risks. In: Journal of Electronic Testing, pp 183-201
54.
Zurück zum Zitat Liu W, Chang CH, Wang X, Liu C, Fung JM, Ebrahimabadi M, Karimi N, Meng X, Basu K (2021) Two sides of the same coin: boons and banes of machine learning in hardware security. In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp 228-251 Liu W, Chang CH, Wang X, Liu C, Fung JM, Ebrahimabadi M, Karimi N, Meng X, Basu K (2021) Two sides of the same coin: boons and banes of machine learning in hardware security. In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp 228-251
55.
Zurück zum Zitat Tan B, Karri R (2020) Challenges and new directions for AI and hardware security. In: IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp 277-280 Tan B, Karri R (2020) Challenges and new directions for AI and hardware security. In: IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp 277-280
56.
Zurück zum Zitat Darjani A, Kavand N, Rai S, Kumar A (2023) Discerning limitations of GNN-based attacks on logic locking. In: Design Automation Conference (DAC), pp 1-6 Darjani A, Kavand N, Rai S, Kumar A (2023) Discerning limitations of GNN-based attacks on logic locking. In: Design Automation Conference (DAC), pp 1-6
57.
Zurück zum Zitat Li M, Khan S, Shi Z, Wang N, Yu H, Xu Q (2022) DeepGate: learning neural representations of logic gates. In: ACM/IEEE Design Automation Conference (DAC), pp 667-672 Li M, Khan S, Shi Z, Wang N, Yu H, Xu Q (2022) DeepGate: learning neural representations of logic gates. In: ACM/IEEE Design Automation Conference (DAC), pp 667-672
58.
Zurück zum Zitat Wang Z, Bai C, He Z, Zhang G, Xu Q, Ho T-Y, Yu B, Huang Y (2022) Functionality matters in netlist representation learning. In: ACM/IEEE Design Automation Conference (DAC), pp 61-66 Wang Z, Bai C, He Z, Zhang G, Xu Q, Ho T-Y, Yu B, Huang Y (2022) Functionality matters in netlist representation learning. In: ACM/IEEE Design Automation Conference (DAC), pp 61-66
59.
Zurück zum Zitat Yasaei R, Yu S-Y, Naeini EK, Faruque MAA (2021) GNN4IP: graph neural network for hardware intellectual property piracy detection. In: ACM/IEEE Design Automation Conference (DAC), pp 217-222 Yasaei R, Yu S-Y, Naeini EK, Faruque MAA (2021) GNN4IP: graph neural network for hardware intellectual property piracy detection. In: ACM/IEEE Design Automation Conference (DAC), pp 217-222
60.
Zurück zum Zitat Chowdhury AB, Bhandari J, Collini L, Karri R, Tan B, Garg S (2023) ConVERTS: contrastively learning structurally invariant netlist representations. In: ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp 1-6 Chowdhury AB, Bhandari J, Collini L, Karri R, Tan B, Garg S (2023) ConVERTS: contrastively learning structurally invariant netlist representations. In: ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp 1-6
61.
Zurück zum Zitat Navada A, Ansari AN, Patil S, Sonkamble BA (2011) Overview of use of decision tree algorithms in machine learning. In: IEEE control and system graduate research colloquium, pp 37-42 Navada A, Ansari AN, Patil S, Sonkamble BA (2011) Overview of use of decision tree algorithms in machine learning. In: IEEE control and system graduate research colloquium, pp 37-42
62.
Zurück zum Zitat Quinlan JR (1986) Induction of decision trees. In: Machine learning, pp 81-106 Quinlan JR (1986) Induction of decision trees. In: Machine learning, pp 81-106
65.
Zurück zum Zitat Khosla C, Saini BS (2020) Enhancing performance of deep learning models with different data augmentation techniques: a survey. In: International Conference on Intelligent Engineering and Management (ICIEM), pp. 79-85 Khosla C, Saini BS (2020) Enhancing performance of deep learning models with different data augmentation techniques: a survey. In: International Conference on Intelligent Engineering and Management (ICIEM), pp. 79-85
66.
Zurück zum Zitat Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 677-692 Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 677-692
67.
Zurück zum Zitat Yang S (1991) Logic synthesis and optimization benchmarks user guide version 3.0. In: Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis Yang S (1991) Logic synthesis and optimization benchmarks user guide version 3.0. In: Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis
69.
Zurück zum Zitat Davidson S (1999) ITC’99 benchmark circuits - preliminary results. In: International Test Conference (ITC), pp 1125-1125 Davidson S (1999) ITC’99 benchmark circuits - preliminary results. In: International Test Conference (ITC), pp 1125-1125
Metadaten
Titel
Machine Learning-Based Security Evaluation and Overhead Analysis of Logic Locking
verfasst von
Yeganeh Aghamohammadi
Amin Rezaei
Publikationsdatum
22.01.2024
Verlag
Springer International Publishing
Erschienen in
Journal of Hardware and Systems Security
Print ISSN: 2509-3428
Elektronische ISSN: 2509-3436
DOI
https://doi.org/10.1007/s41635-024-00144-8