The impact of DC-bus impedance on the switching performance of low-voltage silicon power MOSFETs

Considering the beforehand described effects of the commutation, this section describes the impact of adding the DC-bus snubber characteristic to the original DC-bus impedance as seen from the commutation current. Especially, in low-voltage applications, ceramic DC-bus capacitors are used to stabilize the DC-bus voltage by storing the amount of charge needed for a given voltage drop during transient events. Therefore typical package size is large (e.g., case code 2220 has a size of \({5.7}\times{5.0}\times{3.5}\,\mathrm{mm}^{3}\)) and it is difficult to be mounted close to the switching device/cell. On the other hand, the capacitors of the DC-bus snubber have to be small from a mechanical point of view, so that they could be fit very close to the power switches. Moreover, they should exhibit low parasitic inductance, so that they still provide low impedance especially in the frequency range where the ringing is expected to happen. While the perfect resistance value is already defined by Eq. 2, the optimal capacitance value is still unknown. Therefore some simulations of the DC-bus impedance as seen by nodes A and B in Fig. 2 were carried out. For the simulation, typical parameters for the DC-bus voltage of 60 V were selected, as well as a maximum switched current of 40 A. These values are based on a recent high power density battery charger application [5] to supply an intermediate voltage rail. First, the parts according to Table 1 were considered for simulation without any snubber circuit. It only contains the main DC-bus capacitors \(\mathrm{C}_{\mathrm{B}}\), including its parasitics, as well as the PCB plane capacitance and inductance. The result of this simulation is shown in Fig. 3 in blue. Clearly, the impedance characteristic of eight parallel connected DC-bus capacitors can be seen as well as the peak at 100MHz representing the resonance between the capacitors parasitic inductance, PCB inductance and the PCB capacitance, thus resulting in a ringing at the mentioned frequency.

The red curve of the same figure is related to the simulation model with eleven snubber elements, whose parameters are also reported in Table 1. Comparing the two simulation results, one can notice a significant difference in the high-frequency range due to the frequency shaping of the snubber network. In particular, the resonance at 100MHz is completely eliminated and the magnitude of the impedance around that frequency range is absolutely reduced. A highly damped additional resonance is present in the red curve at a lower frequency due to the additional capacitive contribution of the snubber network. Additionally the impedance shows now a significant resistive behaviour illustrated in Fig. 3. This is provided from the series damping resistors for lowering resonance currents.

The different possible positions of the snubber networks has not been considered for this analysis, as the parasitic contribution of the DC-bus on the overall inductance could be neglected as it is made out of interleaved ground and power planes, and the considered frequency range is well below any kind of wave effects.

The choice of the number of snubber elements which should be considered and simulated is a degree of freedom that could be exploited in order to reduce the peak voltage overshoot \(\Delta u_{sw}\).

High fidelity modeling and simulation of the DC-bus impedance and evaluation of the contribution of the snubber network requires an accurate characterization of the actual frequency dependant model of each component adopted in the circuit, i.e., including all their parasitics. Impedance measurements were performed using a Keysight E4990A Impedance Analyzer and approximated based on an equivalent model for each component individually according to Fig. 2.

Table 1 gives a detailed overview of the measured results and equivalent lumped model parameters. While the parameters of the individual component parasitics and PCB plane capacitance can be easily measured or simulated, the parasitic inductance of the PCB is more difficult to obtain. To overcome this problem, it was decided to measure first the PCB plane capacitance alone, then the main DC-bus capacitors were soldered in and the impedance with the analyzer has been measured by probing directly on the pads A and B, shown in Fig. 2. The results of this measurement exhibits a resonance frequency which can be used to calculate back an estimate of the plane inductance \(\mathrm{L_{PCB1}}\). \(\mathrm{L_{PCB2}}\) represents the inductance of the small distance between the measurement points A and B to the MOSFETs, it was estimated that the value is in the \(\mathrm{pH}\) range and therefore the element was neglected for the analysis within this paper.

The test hardware used for evaluating the performance consists of an eight layer PCB containing several power and ground planes which are interleaved to minimize the equivalent inductance and maximize the DC\(+\) to DC\(-\) plane to plane capacitance. The switching cell arrangement is shown in Fig. 4 and highlights the position of the snubbers \(\mathrm{R_{S,1}}\) and \(\mathrm{C}_{\mathrm{S,1}}\) next to the power transistors \(\mathrm{T_{xS,y}}\) (\(\mathrm{x=H,L;y=1,2}\)) which are placed in a crossover configuration.

While the bottom layer of the PCB is used to connect the individual devices to each other, the layer immediately above acts as a ground plane and is connected to the negative DC-bus to provide a return path for the current. The top side of the PCB is shown in Figs. 5 and 6, where the different placement variations of the main DC-bus capacitors are considered and highlighted (distributed and concentrated), while the gate driver, the main switching inductor, and supply cables were kept at the same position.

In Fig. 5 the optimal solution for placing the main DC-bus capacitors is considered, i.e., they are distributed throughout the switching cell and directly placed at its opposite side, thus reducing the parameter \(\mathrm{L_{PCB1}}\) to approximately its minimum value. On the other hand, the arrangement reported in Fig. 6 considers a concentrated placement of those capacitors, approximately 2 cm away from their ideal position and stacked in the vertical direction to represent a high area density assembly case.

As shown in Fig. 4 the DC-bus snubbers are placed next to the MOSFETs in pairs of two. Still, the test PCB contains more switching cells, which are actually not used. Even though it was considered to place snubbers next to them, because of the influence on the impedance of the DC-bus. The impact of distributed snubbers have been evaluated by considering the probing position shown in Sect. 3.3.

Measurements have been made using passive probes with a bandwidth of 500 MHz for the gate signal, DC-bus and switch node voltages, whereas 1 GHz low-voltage active differential probes have been used to measure the voltage across the snubber resistors, providing a rough estimation of the conducted current through the snubber cell. Fig. 7 shows the test setup including probes.

To verify the effectiveness of the proposed impedance shaping approach, this section builds from the component level impedance measurements in Sect. 3, which aimed to extract the equivalent model of each component considered in the simulation, to total impedance measurements performed at PCB level.

The test PCB has been assembled with the snubber networks on the bottom side, as shown in Fig. 4, and the main DC-bus capacitors according to the layouts in Figs. 5 and 6 (i.e., the already discussed distributed and concentrated cases, respectively).

The first issue that should be considered when approaching these type of measurement is the design of a proper test setup for obtaining the required accuracy and in-field calibration of the probing. In fact, according to the simulation results, a very low value of the DC-bus impedance can be expected over the considered frequency range, with an increase of the real part of the impedance above 20 MHz to values in excess of 0.1 \(\Upomega\).

A custom in-field test fixture was designed and built which compensates the distance between the probing positions A and B (as shown in Fig. 4) and the impedance analyzer properly. The test fixture with the two probing points C and D is illustrated in Fig. 9.

The probe is soldered onto a solid copper sheet to allow the initial short calibration, while the open calibration is performed by lifting the measurement points C and D from the sheet, and connecting each individual source and measure signals together with a small soldering joint. After completing the calibration procedure, the measurement points (both source and measure) have been soldered onto the desired PCB nodes A and B for impedance measurements.

The obtained results are shown in Fig. 8 for two cases: when the snubber networks are not mounted (Fig. 8a), and when they are (Fig. 8b). Additionally the simulation results of Fig. 3, characteristic curves of the magnitude, phase and real part of the impedance \(\mathrm{Z}\) as seen from the A and B terminals are reported. Three curves are plotted: simulated impedance (red curve), measured impedance with concentrated DC-bus capacitors (blue curve), and measured impedance with distributed DC-bus capacitors (green curve).

Fig. 8a shows that the experimental curve without snubbers and concentrated placement. The simulated curve match almost perfectly, as the simulation model is indeed a concentrated one. The experimental result with distributed placement highlights that quite a huge reduction of the impedance is achieved in a wide frequency range, providing beneficial effects on the switching behavior. Also, several resonance points between 700 kHz and 3 MHz are present in both cases (without and with the snubber networks), as concentrated DC-bus capacitors are resonating between each other because of the vertical stacking.

From the results of Fig. 8b it can be clearly seen that for the concentrated placement of the DC-bus capacitance the snubbers are fulfilling the expectations above 10 MHz, with an anti-resonance frequency at 18.6 MHz compared to the expected 19.5 MHz. Additionally, the peak impedance at this anti-resonance frequency is lower than expected from simulation (0.25 \(\Upomega\) compared to 0.49 \(\Upomega\)), resulting in a reduced overshoot when charging and discharging the DC-bus snubbers from the main DC-bus capacitors.

Additional remarks on the results shown in Fig. 8: any impedance measurement is very sensitive to variation of the probing position and connection of the probing points. As a result, the impedance of the test setup with distributed DC-bus capacitors including snubber networks seems to be higher than the setup without, which is not expected. This result in an inductance difference below 500 pH, representing the lower boundary of the measurement accuracy.

In this section time domain transient responses of the different configurations of the test circuit are reported, as obtained by double pulse tests, whose setup is shown in Fig. 12. The aim is to verify the switching performance with respect to peak switch node voltage \(u_{\mathrm{SW}}\) overshoot, ringing frequency and DC-bus voltage \(u_{\mathrm{HB}}\) drops. All the tests consider the same DC-bus voltage of 60 V and the same pulse patterns to get comparable results for different scenarios: modifying the test PCB according to Fig. 6 without any DC-bus snubber network close to the power MOSFETs at the switching cell; same placement of the main DC-bus capacitors, but snubber networks have been added close to the power MOSFETs. The results which show the impact of those modifications are shown in Fig. 10. In addition a second scenario has been investigated which considers that the main DC-bus capacitors have to be rearranged, resulting in a distributed placement of them on the top side of the PCB as shown in Fig. 5. For this case three further modifications have been considered: the snubbers stay in place; the snubbers will be removed; the snubbers are replaced by two main DC-bus capacitors. Mechanical details are represented in Fig. 13 whereas Fig. 11 shows the corresponding measurement results. In general, we have considered different switching conditions in the different tests, namely zero current switching, hard commutation and zero voltage switching.

A commercial inductor (Würth Elektronik 7443763540068) with 6.8 \(\upmu\)H was connected between the switching node and the negative DC-bus. Probing positions are shown in Fig. 7.

The sequence of pulses was designed in order to have roughly 40 A flowing into the inductor, while a hard commutation is performed.

The results of the first test setup are reported in Figs. 10abc and refer to the concentrated (and therefore non-ideal) placement of DC-bus capacitors and no snubber network case. While for zero current switching no significant overshoot can be identified, the voltage overshoot during hard switching results in a large overshoot of about 21.2 V both at the switching node (red trace), and on the DC-bus voltage \(\mathrm{u_{HB}}\) (blue trace). This can be explained as, for zero current switching only \(\mathrm{C}_{\mathrm{oss}}\) of the power MOSFETs has to be charged, whereas the reverse recovery charge during hard commutation makes a significant difference in the switching transition. The voltage across main DC-bus capacitors \(\mathrm{C}_{\mathrm{B}}\) is only slightly affected, therefore the voltage drop has to occur on the longitudinal inductances \(\mathrm{L_{CB}}\), \(\mathrm{L_{PCB1}}\) and \(\mathrm{L_{PCB2}}\), resulting in stored energy, which will get transferred to the output capacitance \(\mathrm{C}_{\mathrm{LS}}\) of the low-side MOSFET, causing the peak overshoot in voltage and resonance at about 91.7 MHz. This resonance can be seen during zero voltage switching too, which is illustrated in Fig. 10c. Obviously, the magnitude of the peak DC-bus voltage overshoot is significantly smaller, because the longitudinal inductance only has to conduct the current being switched, thus the stored energy is less. The resonance frequency measured with the transient method is slightly smaller than the predicted one (100 MHz) according to Fig. 3 (blue), which is a result of neglecting the package inductance of about 200 pH per device and \(\mathrm{L_{PCB2}}\).

By adding the paralleled DC-bus snubbers, the longitudinal commutation loop inductance will not only be reduced, but an additional resistive characteristic will be introduced, thus allowing an effective damping of any resonance and pushing the resonance frequency upwards. The impact of this measure is shown in Figs. 10def for the DC-bus and switching node voltage. Figs. 10ghi show the current through the snubber network at probing position 1 and 2 according to Fig. 7.

As expected from the DC-bus impedance simulations, the resonance frequency at 100 MHz which was measured with 91.7 MHz is pushed upwards to 181 MHz, which was barely modeled in the simulation and impossible to be validated with a 120 MHz impedance analyzer, like the one adopted in the experiments. The anti-resonance point which is expected to be at about 19.5 MHz, was measured at 20.5 MHz, which is slightly above. More important is the overshoot of the switching node voltage. This has decreased from 21.2 V down to 5.1 V, being a major improvement considering a 60 V DC-bus voltage. But still, the expected aperiodic recharging behaviour of the DC-bus snubber capacitors could not be perfectly achieved, which results from imperfect modeling especially of the PCB power and ground planes. This will also explain why the current \(i_{\mathrm{S}}\) (according to Fig. 1) through the snubber 2 (away from the power MOSFETs) is lagging in time due to additional inductance compared to the current through the snubber 1 (very close to the MOSFETs). Comparing zero voltage switching results (Fig. 10c to Fig. 10f) the benefits of using DC-bus snubber networks are clearly visible too. The peak overshoot as well as the ringing will be damped.

While the first setup takes a non-ideal placement of the main DC-bus capacitors \(\mathrm{C}_{\mathrm{B}}\) into account, the second test setup considers a distributed placement of the main DC-bus capacitors according to Fig. 5. Fig. 11 shows the corresponding transient measurements with respect to three additional modifications which are illustrated in Fig. 13. First the snubbers are still in place supporting the stabilization of the DC-bus at the switching cell. As expected, this configuration result in a low amount of total commutation loop inductance, therefore voltage overshoots are minimized to only 1.7 V, and the ringing is well damped while the frequency at which it occurs is 196 MHz. Figs. 11abc show these results while Fig. 5a represents the mechanical setup. For the second test, the DC-bus snubbers were removed to see the impact of the snubbers, while having the main DC-bus capacitors placed very distributed on top of the PCB, like shown in Fig. 13b. Eliminating the snubbers will have the consequence that the commutation path goes through the PCB only, with the consequence that the commutation loop inductance slightly increases. Fig. 13b also gives insights into the PCB layer stackup indicating the DC\(+\) layers in red, DC\(-\) in blue and the switch node in orange. Figs. 11def represent the according measurements and indicates that not only the ringing frequency decreases form 196 MHz to 156 MHz, also the DC-bus voltage measured at the switching cell increases from 5.2V to 12V . The third alternative is the very close placement of the main DC-bus capacitors on the same side where the switches are placed. While this setup is very common for bottom side cooled semiconductors, it adds additional mechanical constrains in case top side cooled devices are used. The height constrain of each component has to be considered. Especially when the power semiconductors have a smaller height compared to the main DC-bus capacitors, special measures must be taken into account. Therefore Fig. 13c represents one solution. Hence, the difference in height cannot be compensated with a thicker Thermal Interface Material (TIM), the heatsink has to be milled where the capacitors are placed. This does not only impact the thermal heat dissipation properties, it adds additional mechanical constraints e.g. positioning. From an electrical performance point of view, the voltage overshoot during hard commutation is similar compared to the setup with snubbers. Details are shown in Figs. 11ghi. Comparing the results for the shown modifications, clearly the overshoot can be significantly reduced when implementing DC-bus snubbers near by the switching transistors. Due to the small size of those components they can easily be mounted and no additional mechanical measures are needed.