A 0.46–0.52-THz fully-differential quasi-monostatic FMCW radar transceiver in 90-nm SiGe BiCMOS

Radar applications benefit from the large achievable bandwidths in the terahertz (THz) frequency range, resulting in a range resolution in the single-digit millimeter range. Traditionally, terahertz frequencies have been explored using split-block designs with III‑V compound semiconductor Schottky diode frequency multiplier and driving amplifier chains. Although these designs achieve the highest performance in terms of noise figure and output power, the overall system size and scalability for low-cost mass-market deployment in a compact demonstrator is challenging. One example of such a diode multiplier-based split-block design is a vector network analyzer (VNA) frequency extender module which has been utilized at 0.85–1.1 THz [2] and at 1.1–1.5 THz [3] for radar operation typically occupying at least 20 cm in the largest dimension with a mass towards the kilogram range. Additionally, custom split-block radar designs have been demonstrated at 0.58 THz [4] and 0.675 THz [5] using GaAs Schottky-diode multipliers, with system sizes comparable to the VNA frequency extender modules.

In comparison, low-cost silicon-integrated technologies such as SiGe bipolar CMOS (BiCMOS) and CMOS have been outlined as a viable technology option [6] for future mass-market terahertz designs. Nevertheless, these production technologies in silicon only reach \(f_{\text{max}}\) of around 500 GHz, with recent advancements in SiGe BiCMOS achieving \(f_{\text{max}}\) of 670 GHz [7]. The performance is considerably lower compared to III‑V technologies which have shown power amplification at 1 THz [8] with \(f_\textit{T}/f_{\text{max}}\) of 0.61/1.5 THz indium phosphide HEMTs. This trend is illustrated in Fig. 1, where saturated output power measurements of power amplifiers above 500 GHz have only been shown in III‑V technologies, with silicon-integrated power amplifiers plateauing around 300 GHz.

Therefore, there is a strong interest to fill the perceived terahertz gap in silicon-integrated technologies using transceivers with high integration levels for a compact and low-cost system demonstrator. Currently, state-of-the-art frequency-modulated continuous-wave (FMCW) radar transceivers in silicon-integrated technologies have been shown at 220–320 GHz in 65-nm CMOS [9], at 311–338 GHz [10], at 367–382 GHz [11] in 130-nm SiGe BiCMOS. More recently, a FMCW radar demonstrator was introduced at 0.45–0.49 THz in a monostatic configuration [12].

This paper proposes a 90-nm SiGe BiCMOS fully-differential quasi-monostatic 0.46–0.52-THz FMCW radar transceiver. Fully-differential dual-stacked patch antennas are integrated on chip, removing the otherwise required lossy, hard-to-model and unfeasible chip-to-board or chip-to-package interface. The \(f_\textit{T}\) and \(f_{\text{max}}\) of the technology is 300 GHz and 480 GHz, respectively. This work is able to further extend the frequency range of the 240-GHz radar transceiver architecture [13] consisting of a fully-differential quadrature push–push doubler at the transmitter (TX) and a fully-differential subharmonic dual-stacked switching quad mixer [14] at the receiver (RX). Nevertheless, with this work, we are able to demonstrate subharmonic operation up to and beyond the technology’s \(f_{\text{max}}\) of 480 GHz. The previously implemented radar transceiver [13] in a prior-generation technology with an \(f_\textit{T}/f_{\text{max}}\) of 250/370 GHz was operating well below the \(f_{\text{max}}\) at 240 GHz. Although the single-ended monostatic architecture [12] is able to achieve a smaller area, it is limited in terms of the maximum permissible output power due to poor TX-RX isolation in the dual-use frequency doubler and subharmonic mixer circuit. When considering future improvements in SiGe BiCMOS [7] the proposed fully-differential quasi-monostatic architecture, expanded from [15] can accommodate future power amplifiers at the transmitter given a simulated 57 dB isolation between TX and RX antennas. The measured effective isotropic radiated power (EIRP) is \(-\)8.8 dBm at 0.47 THz and the measured single-sideband noise figure (\(\text{NF}_{\text{SSB}}\)) is 25.2 dB at 0.471 THz.

The overall transceiver architecture is illustrated in Fig. 2a and consists of a frequency multiplier-based approach. At 20 GHz, an off-chip local oscillator (LO) signal originating from a phase-locked loop (PLL) synthesizer is applied as the input of the 0.48-THz transceiver. The first block, grouped as a \(\times 6\) frequency multiplier consists of a one-transistor active balun, a cascoded differential pair tripler and a bootstrapped frequency doubler from [16], depicted in Fig. 3 to achieve a 120-GHz signal. The TX-RX LO path is divided using a 120-GHz fully-differential branchline coupler. After the TX-RX division, a further bootstrapped frequency doubler circuit multiplies the LO frequency to 240 GHz on both the RX and TX path. On the TX side, a quadrature push–push doubler architecture is chosen to achieve a differential signal at 0.48 THz. The required \(90^{\circ}\) phase shift between the inputs of the two parallel common collector push–push doublers detailed in Fig. 4a, is achieved using a 240-GHz fully-differential branchline coupler. The 0.48-THz quadrature doublers, are driven by three stages of amplifiers to compensate for insertion losses of the 240-GHz branchline coupler.

The subharmonic mixer on the RX side, depicted in Fig. 4b uses a dc-connection to the on-chip RX antenna array. The mixing process is essentially divided into two parts. First the 0.48-THz RF signal is downconverted by the bottom quad driven with a 240-GHz LO signal to an IF around 240 GHz. In a second step the IF output of the first quad is further downconverted to the desired IF around dc by the second quad which is also driven with a 240-GHz LO signal.

In Fig. 5a, a single stage 240-GHz amplifier is illustrated. The amplifier uses a differential dual-stacked common base topology for improved gain. Input matching is accomplished using \(\text{TL}_{\text{1}}\) with 30 \(\upmu\)m, a series 15-fF capacitor and \(\text{TL}_{\text{2}}\) with 36 \(\upmu\)m. To ensure stability from dc to well above the operating frequency, MOMCAPs of 50 fF are placed at each of the emitters of the input transistors \(\text{Q}_{\text{1}}\) and \(\text{Q}_{\text{2}}\). Gain-boosting is introduced at the base of the input transistors \(\text{Q}_{\text{1}}\) and \(\text{Q}_{\text{2}}\) using \(\text{TL}_{\text{3}}\) with 20 \(\upmu\)m. \(\text{TL}_{\text{4}}\) with 15 \(\upmu\)m and the differential line \(\text{DL}_{\text{1}}\) with 15 \(\upmu\)m further help to boost the gain of the amplifier. Overall, the amplifier shows simulated gain of around 8 dB per stage with typical 3‑dB bandwidths less than 20 GHz. For this reason, 3 stages are implemented in the TX path to guarantee a saturated output power of around 3 dBm, considering insertion losses of the 240-GHz branchline coupler and transmission lines and limited output power of the 240-GHz frequency doubler.

The current mirror, depicted in Fig. 5b is directly connected to the input transistors, while the cascode bias voltages are derived from a resistive divider integrated into the same current mirror reference path formed by \(R_{\text{1}}\) and \(R_{\text{2}}\). \(R_{\text{1}}\) and \(R_{\text{2}}\) together set the bias current. Differential circuits have two mirrors to improve layout symmetry. The emitter resistor \(R_{\text{E}}\) is sized accordingly for the current mirror factor. A one-to-one current mirror is implemented in Fig. 4 and a one-to-four current mirror is designed in Figs. 3 and 5a.

The wire-bonded 0.48-THz transceiver is characterized using an over-the-air measurement setup, depicted in Fig. 7. The 26-dBi standard gain horn antennas attached to R&S ZC500 VNA frequency extenders have a distance of 26 cm to the transceiver chip to ensure farfield conditions. The signal input to the transceiver chip is a APSIN26G source. Two R&S ZC500 VNA frequency extenders are used for TX and RX characterization. The first frequency extender is used as a transmitter with its output power characterized by an Erickson PM4 power meter. The first frequency extender is then connected to the second frequency extender that is used as a receiver. In this way, the receiver conversion gain can be determined of the second frequency extender. A APSIN26G is used as the RF-source for the transmitting R&S ZC500 frequency extender. The receiving R&S ZC500 frequency extender is connected to the R&S FSIQ-26 signal analyzer. The LO signal from an Agilent E8257D signal source is connected to the receiving R&S ZC500 frequency extender. The 240-GHz branchline coupler has been characterized and compared to simulations in Fig. 8. A meandered design was implemented to achieve a compact layout. Simulated and measured insertion loss and phase shift are in good agreement at 240 GHz. The measured and simulated normalized antenna gain patterns are given in Fig. 9. Simulation and measurement agree well within 2–3 dB in the RX antenna, although the measured TX antenna \(E\)-plane deviates from simulation, perhaps due to a relative phase imbalance in the two quadrature paths prior to the 0.48-THz push–push common collector frequency doublers. A peak system conversion gain (CG) of 7 dB and a \(\text{NF}_{\text{SSB}}\) of 25.2 dB at 0.471 THz have been measured in Fig. 10a. The gain method [17] is used to determine the noise figure as no external noise source could be found at these frequencies. In Fig. 10b an EIRP of \(-\)8.8 dBm is measured at 0.47 THz. Using the EIRP measurement and the simulated realized antenna gain results in a calculated output power \(P_{\text{out}}\) of \(-\)15.8 dBm at 0.47 THz. The harmonics separated by 20 GHz are at least 30 dB below the carrier, as illustrated in Fig. 10c when a 20-GHz signal is fed into the transceiver. The phase noise performance is considered in a two step process. First, the 20-GHz signal from a APSIN26G source was directly connected to the R&S FSIQ-26. Afterwards, the 20-GHz APSIN26G source was connected to the transceiver. The multiplied transmitted signal was received by the R&S ZC500 frequency extender and downconverted to an IF signal, input to the R&S FSIQ-26. In Fig. 10d the phase noise translation due to a multiplication factor of 24 follows the theoretical 27.6 dB, within a 2-dB range.

Fig. 11a depicts the FMCW radar measurement setup using the demonstrator on-board frequency source and a single 1‑cm trihedral reflector target at around 11.5 cm. When considering the \(\times 24\) multiplication factor of the transceiver, a 60-GHz RF bandwidth is achieved using a linear frequency sweep at the input LO from 19.3 GHz to 21.8 GHz in 1 ms. More details on the similar demonstrator platform are described in [12, 13]. The achieved range resolution can be estimated from Fig. 11b by examining the distance between the peak and the first null [18]. The peak-to-null distance is 6.5 mm in Fig. 11b. In the measurements, a Hann window is used to improve sidelobe supression at the cost of a 2 times larger peak-to-null width compared to the boxcar window. Therefore a calculated range resolution of 3.25 mm is determined, while the theoretical range resolution is given as at a 60-GHz sweep bandwidth \(B_{\text{sw}}\).

Table 1 details the current state-of-the-art FMCW radar demonstrators above 0.3 THz in silicon-integrated technologies. The 100-GHz bandwidth in [9] comes at the cost of a second fixed 10-GHz LO signal, generated using a laboratory source. The 10-GHz LO signal is used to create the frequency shifts of the five individual 20-GHz bandwidth comb channels. In [10] a two-chip solution demonstrates an increased dc power consumption and a larger system size and cost when compared to a single-chip transceiver. In [19] a quasi-monostatic transceiver is proposed that uses a single-ended TX and a differential RX. A comparable EIRP to this work of around \(-\)10 dBm is achieved at 0.46 THz, nevertheless in a SiGe BiCMOS technology with f_T/f_max of 470/650 GHz. An on-chip free-running voltage-controlled frequency source is used in the FMCW radar measurements in [11], which results in a highly non-linear frequency ramp. This work is the first demonstration of a fully-differential quasi-monostatic FMCW radar transceiver at 0.48 THz. The transceiver is integrated in a compact credit card-sized demonstrator, using an on-board off-the-shelf frequency source at around 20 GHz. With this work, the operating frequency of silicon-integrated radar transceivers is further extended beyond 0.5 THz. The measured system noise figure compares well with silicon-integrated FMCW radar transceivers above 0.3 THz.

A 0.46–0.52-THz fully-differential quasi-monostatic FMCW radar transceiver has been implemented in a 90-nm SiGe BiCMOS technology with an \(f_\textit{T}/f_{\text{max}}\) of 300/480 GHz. The transmitter achieves a measured EIRP of \(-\)8.8 dBm at 0.47 THz and the receiver demonstrates a measured conversion gain of 7 dB and a measured single-sideband noise figure of 25.2 dB at 0.471 THz. A power amplifier with more than 6 dBm of output power at 300 GHz has been shown in [7] using a SiGe BiCMOS technology with \(f_\textit{T}/f_{\text{max}}\) of 470/650 GHz, motivating a further extension of the operating frequency of the radar transceiver to 0.6 THz using the proposed fully-differential subharmonic architecture.