Detector development for particle physics

The DMAPS sensor developed withing the RD50 collaboration is implemented in the Lfoundry \(150\,\text{n}\text{m}\) (LF15A) process. A cross-section through the process is given in Fig. 1. The sensor uses a fully depleted substrate for particle detection. The depletion is attained by applying a high voltage between the front side electronics and a backside electrode attached to the thinned-down substrate. Charge collection is performed using the large collection electrode approach. The depletion zone is isolated from the readout electronics via a very deep n‑well which can be positioned below a deep p‑well enabling isolation of both n‑mos and p‑mos transistors. This is one of the features of the LF15A process [17].

The pixel size of the chip is 62 \(\times\) 62 \(\mathrm{\upmu\text{m}^{2}}\). The output of a large collection electrode is amplified using a charge sensitive amplifier and shaped. A comparator is used to detect a particle transition. In the case of such an event the status of the global clock is stored in the in-pixel random access memory (RAM) to enable time stamping and time-over-threshold (ToT) measurements. Pixels are read out via a shared column bus, where the in-pixel logic enables pixel masking to prevent dead pixels from blocking the column bus. Each column has an EOC circuit in which events are stored and made available for readout via a wishbone bus. The time resolution of the application specific integrated circuit (ASIC) is 40 ns [19].

The EOC features two readout modes: The first mode uses a simple priority logic, where pixels with a higher address are prioritized. As a consequence those with lower addresses are more susceptible to loosing events in high-occupancy situations. Therefore, an alternative mode, the so-called FREEZE mode, was implemented where the readout of each pixel is frozen until the whole double column has been read out which leads to equal treatment of all pixels. The data from an event generated in a pixel consist of timestamps for the leading and trailing edges and the pixel address [17].

The OBELIX sensor is implemented in the TowerJazz \(180\,\text{nm}\) process. In contrast to the RD50-MPW3 ASIC the design utilizes a small collection electrode [20]. The OBELIX sensor is one of four proposals for the (partial) replacement of the VTX detector of the BELLE‑2 experiment. OBELIX is derived from the existing TJ-Monopix2 chip. The sensor will feature a pixel pitch between 30–\(40\,{\upmu}\text{m}\) and a timestamp accuracy of \(25\,\text{n}\text{s}\). In contrast to TJ-Monopix2, OBELIX will have a triggered readout architecture enabling a trigger rate of up to \(30\,\text{kHz}\). [6]

SiC has the favorable property that its dark current does not substantially increase after an exposure to ionizing radiation. We measured the current through 3 \(\times\) 3 \(\mathrm{\text{m}\text{m}^{2}}\) SiC particle detectors containing a \(50\,\upmu\text{m}\) thick epitaxial layer before and after neutron irradiation with fluences up to \(10^{16} \textrm{n}_{ \textrm{eq}}/ \textrm{cm}^{2}\) [21]. The measurement results of un-irradiated and irradiated detectors are given in Fig. 2. They reveal, that the dark current remains below \(1\,\text{p}\text{A}\) \(\text{mm}^{-2}\) in all cases. A comparison to the current spike generated when a single particle passes through the detector (at least \(0.5\,\upmu\text{A}\)) shows, that the dark current is negligible even for large detector areas. Consequently, the readout circuit does not need current compensation when accessing the detector. It further enables, if desired, a DC coupling between detector and readout circuit.

This property enabled us the development of sensors that can detect both single particles and particle fluxes, where single particles can not be discriminated anymore. We are aiming to deploy such a device at Medaustron, a cancer treatment center, which provides various particle rates: In the kHz range particle detector tests are run, whereby detectors such as the RD50-MPW5 are exposed to beams of varying intensity and energy to verify their performance. In this mode, single particle counting is realized by detecting current spikes. Particle-rates in the GHz range are used for patient treatment and biological research. Non-SiC based beam monitors currently in operation at Medaustron are only able to operate either at clinical rates or in single particle detection mode up to approx. \(5\,\text{M}\text{Hz}\), while the novel SiC based monitors will be able to handle both simultaneously.

Due to process limitations, i.e., the absence of advanced complementary metal-oxide-semiconductor (CMOS) processing options, SiC is still restricted to passive sensors, e.g., strip detectors, or HPS. Nevertheless, for passive sensors suitable processes, for example the dedicated process for SiC detectors developed by CNM are already available [22]. The process developed by CNM consists of a single p‑implant into the n‑substrate and a single metal layer. Consequently, only five masks are required, leading to low costs for prototype production. A cross-section through the process is given in Fig. 3. Together with CNM we have designed several test vehicles for radiation hardness studies and numerous prototype strip detectors for our beam monitor.

Two approaches can be followed when building a particle detector that can work from the kHz to the GHz range. The first approach is to split the frequency range in parts. For low frequencies, the detector counts events from single particles impinging onto the detector. For higher frequencies, the current through the detector is measured. The detector current is proportional to the particle fluence of the beam. The second approach relies on counting particles over the full range of frequencies. This requires a sufficiently fast front-end for detector readout. We followed both approaches.

For building a readout system that counts particles at low fluences and measures current at high fluences, we employed the AD8488 frontend for X‑Ray panels. This integrated circuit (IC) provides current integrators for 128 channels which have a selectable gain and a nominal equivalent noise charge (ENC) below 1000 elementary charges. For single particle detection, the gain of the AD8488 is set to it’s maximum. For each sample, based on the measured charge we determine if a particle was present or not. At higher particle rates such as clinical rates, the measured charge is taken as a measure for the number of particles passing during the sample integration time. Fig. 4 shows a histogram of detected charges in single particle detection mode. One ADC count corresponds to \(5.5\,\text{a}\text{C}\). It was measured using a SiC pad detector with a \(50\,{\upmu}\text{m}\) thick active zone was hit by protons with an energy of \(62.4\,\text{MeV}\) (corresponding to 5 minimum ionizing particles, MIP). A Landau distribution convoluted with the Gaussian distribution of the noise (Langauss) was fitted to the histogram. The Langauss fit corresponds to the expected charge spectrum in the absence of noise. It can be observed that the signal to noise ratio (SNR) is not yet ideal and MIPs would be undetectable. However, when replacing the SiC pad with a thicker device the signal level is increased. If we simultaneously accept that only a fraction of particles can be detected, it is possible to employ the sensor for single particles detection. Specifically, we are aiming for detectors having a nominally \(100\,\upmu\text{m}\) thick active layer. The SNR for MIPs on this new detectors substrates is expected to be in range between 5 and 6.

The readout circuit was also tested in conjunction with a strip detector. Since our SiC strip detectors are still being manufactured, we used a Si strip having a thickness of 300 \({\upmu}\text{m}\) and a fill-factor of 50%. Fig. 5 shows the measured cross section through the beam, resolved in space and time at a sampling rate of 37 kHz. The nominal average particle rate was 1.6 GHz. The readout was performed using the same front-end as for the single particle case but with reduced sensitivity. It must be noted that after one day of performing measurements using the Si strip detector, the radiation led to a dark current as large as the signal from the high intensity beam, driving the system into saturation. Under the envisioned operating conditions for our SiC sensors we expect a sensor lifetime of more than 2 years.

For counting particles even at higher fluences we are developing a TIA based readout frontend. Commonly detectors are read out by utilizing a charge sensitive amplifiers (CSA) in the input stage. CSA have favourable noise characteristics. For a typical detector capacitance between 1 and 4 pF equivalent noise charges (ENC) below 100 electrons are documented in the literature [23]. However, the limited bandwidth of CSA make them unfavourable for our application. We expect pulses of a duration of \(0.4\,\text{n}\text{s}\) per particle for a \(100\,{\upmu}\text{m}\) thick sensor. Attaching a CSA to such a detector would limit the speed of our frontend. Consequently, we opted for using a transimpedance amplifier (TIA) based readout front-end and optimized it for our SiC strip detectors. Given the limitations of processing technology available for SiC, the TIA is implemented on silicon.

The overall circuit of the detector and the main parasitic components are given in Fig. 6. The detector is connected between the input of the TIA and a high voltage supply (HV). The connection between the detector and the TIA will be established by directly bonding the SiC detector to the silicon TIA, minimizing parasitic resistance and inductance. When simulating the detector the detector was thus modelled as current source (\(I_{D}\)) with a parallel capacitance (\(C_{D}\)) without taking into account parasitic inductances.

We chose a TIA design based on the “inverter with active common-drain feedback” (ICDF) circuit presented in [24]. Compared to the traditional regulated cascode (RGC)-TIA circuit, the ICDF has a larger gain in the feedback path. This reduces the input impedance and suppresses noise. A similar approach was used in [25], where the amplification was improved by introducing two cascodes in the inverter.

The TIA (circuit level implementation shown in Fig. 7) was implemented in a \(130\,\text{n}\text{m}\) silicon CMOS process (Skywater SKY130A). The Skywater SKY130A process was selected due to its compatibility with open source electronic design automation (EDA) tools. The design was developed using exlusively open source EDA tools to reduce tooling costs. Transistor sizes are provided in Fig. 1. Our design goal was to achieve a sufficient bandwidth for detecting the expected current pulses from a \(100\,{\upmu}\text{m}\) thick SiC sensor (at least \(1.2\,\text{G}\text{Hz}\) over all temperatures and corners) while simultaneously minimizing noise and input impedance.

To attain these design goals, a combination of the circuits given in [24] and [25] was implemented. Compared to [25] the smaller process node made the addition of two cascode transistors to the inverter unfavourable. Instead, only one cascode was introduced to the n‑channel part of the inverter, while the cascode was omitted for the p‑mos transistor. When connecting the gate of the cascode transistors directly to VDD and GND, as shown in [25], simulations revealed that process variations cause significant changes in the operating points of M3 and M4. To suppress this effect we introduced a biasing circuit (see Fig. 8). For the process corners with nominal and high threshold voltages, the circuit sets the gate voltage of M3 close to VDD. For process corners where M3 has a low threshold voltages, the gate voltage of M3 is reduced, limiting the transverse current and keeping the drain source voltage of M3 and M4 within acceptable limits. The chosen sizes are again given in Table 1.

The TIA features two outputs: Out1 and Out2 (cf. 7). The authors in [24] used Out1 as the signal was larger. In our design the trans-conductance of M1 was increased to account for the larger input capacitance, reducing the amplitude at Out1. Thus, in our design we employ the output Out2. We chose to employ R1 as transimpedance determining element instead of a transistor as done in [24] and [25]. While a transistor promises to increase the usable bandwidth, precision resistors reduce the process dependence of the trans-impedance. Since our design is not primarily optimized for bandwidth and the use of a resistor did not result in any reduction of bandwidth, we opted for this variant. The chosen value for R1 was \(1.9\,\text{k}\mathrm{\Omega}\).

We also intend to measure DC currents. For this purpose a copy of the TIA were implemented. The copy provides the output voltage of the TIA when no input current is applied. A series of differential amplifiers is used to match the signal to the intended output impedance of \(50\,\mathrm{\Omega}\). Similarly to [24], the differential amplifier chain has 3 stages. It adds up to \(10\,\text{dB}\) of gain to the TIA and has a nominal output impedance of \(50\,\mathrm{\Omega}\). The copy of the TIA was integrated together with the biasing circuit and is shown in Fig. 8. The TIA output for the input of the differential amplifier is given at Out_ref. The Bias voltage for the main TIA is provided at Bias2.

The overall gds layout is shown in Fig. 9. For frequencies up to \(1.2\,\text{G}\text{Hz}\) the input impedance is below \(40\,\mathrm{\Omega}\) for all temperatures. Thus, an input capacitance of up to \(3\,\text{p}\text{F}\) can be permitted. Post layout simulations show that the bandwidth of the TIA including the output driver is between 1.2 and \(1.8\,\text{G}\text{Hz}\) depending on process variations and temperature when loaded with a \(3\,\text{p}\text{F}\) detector capacitance and no output load. The temperature and process dependence of the bandwidth is given in Fig. 10. The simulated input referred noise is shown in Fig. 11. Below \(1.2\,\text{G}\text{Hz}\) it is below \(30\,\text{p}\text{A}\) \(\sqrt{\text{Hz}}\), while a minimum of \(10\,\text{p}\text{A}\) \(\sqrt{\text{Hz}}\) is achieved for frequencies between \(10\,\text{MHz}\) and \(200\,\text{MHz}\). The detector capacitance significantly increased the input referred noise. When no detector capacitance is included in the simulation, the input referred noise was below \(15\,\text{p}\text{A}\) \(\sqrt{\text{Hz}}\). The power consumption of the overall circuit was simulated to be below \(72\,\text{m}\text{W}\) including the output driver. One TIA consumes \(18\,\text{m}\text{W}\) or less. When integrating the TIA into a detector system, we expect to implement 512 TIA channels, resulting in a total power consumption of \(4.6\,\text{W}\).