1 Introduction to open-source IC design
2 Open-source IC design software stack and usage
Tool | Usage | Ref. |
---|---|---|
Xschem | Graphical schematic entry tool for full-custom circuit design incl. waveform viewer | [29] |
ngspice | SPICE-level mixed-mode (analog plus digital) circuit simulator | [21] |
Xyce | High-performance SPICE-level analog circuit simulator with support for large-scale parallel computing | [42] |
Magic | Custom layout editor supporting DRC and parasitic extraction | |
KLayout | Fast custom layout editor with DRC and LVS support | [15] |
netgen | Netlist comparison tool used for LVS | [10] |
osic-multitool | User scripts for DRC, LVS, parasitic extraction (PEX), Verilog linting, etc. | [26] |
Icarus Verilog | Digital simulator and linter for Verilog | [38] |
Verilator | High-performance digital simulator and linter for Verilog | [36] |
Yosys | Digital synthesis tool for Verilog | |
OpenLane | RTL-to-GDS flow (control and configuration scripts) | |
OpenROAD | RTL-to-GDS engine: automatic placement and routing, delay extraction, and static timing analysis | |
SKY130 | SkyWater Technologies 130-nm CMOS open-source PDK | [34] |
3 Circuit design
3.1 Digital-to-analog converter (DAC) matrix
3.1.1 Layer stack considerations
li
and 5 metal routing-layers m1
–m5
. Since the design rules were disadvantageous for an area-efficient design using layer m5
, it was fully dedicated to the top-level power distribution network (PDN). In this case, layers m2
, m3
, and m4
are used for the capacitor layout.m2
–4
, the routing of the decoder circuit as shown in Fig. 6 must be done in the residual layers li
and m1
. Using the local interconnect layer for routing is a compromise to allow the waffle capacitor design on top of the decoder to use three metal layers for best matching performance, but the higher sheet resistance of \(R_{\mathrm{s,li}}=12.8\,{\mathrm{\Omega}/\Box}\) (in comparison to metal layers) could become the limiting factor regarding DAC speed.
3.1.2 Capacitor topology evaluation
Capacitor in Fig. 5 | (a) | (b) | (c) | (d) | (e) | (f) | (g) | (h) |
---|---|---|---|---|---|---|---|---|
Unit caps \(C^{0}\) per cell | 16 | 8 | 8 | 8 | 16 | 8 | 8 | 8 |
Area per cell (\(\mathrm{\mu m^{2}}\)) | 41 | 25 | 23 | 22 | 17 | 24 | 28 | 19 |
Cell cap \(C_{\mathrm{cell}}\) (\(\mathrm{fF})\) | 9.2 | 4.8 | 0.6 | 3.1 | 0.7 | 1.1 | 5.6 | 5.0 |
Unit cap \(C^{0}_{\mathrm{16}}\) (\(\mathrm{aF}\)) | 572 | – | – | – | 46 | – | – | – |
Unit cap \(C^{0}_{\mathrm{8}}\) (\(\mathrm{aF}\)) | 595 | 593 | 76 | 389 | 51 | 134 | 695 | 621 |
Unit cap \(C^{0}_{\mathrm{4}}\) (\(\mathrm{aF}\)) | 637 | 620 | – | 385 | 75 | 173 | 705 | 672 |
Unit cap \(C^{0}_{\mathrm{2}}\) (\(\mathrm{aF}\)) | 720 | 675 | – | 410 | 130 | 240 | 785 | 685 |
Unit cap \(C^{0}_{\mathrm{1}}\) (\(\mathrm{aF}\)) | 870 | 780 | 15 | 440 | 240 | 350 | 960 | 770 |
3.1.3 Semi-differential charge compensation
m2
and the decoder routing layer m1
would be highly preferable to shield parasitic capacitance between the top plate and the dynamic decoder control signals. Still, the lack of available routing layers does not allow adding such a layer in this configuration.col
. The row control signals \(\overline{\mathtt{row}}\) and \(\overline{\mathtt{rowon}}\) have been extended by signal \(\overline{\mathtt{rowoff}}\) with the limitation that exactly one signal is at potential 0 V (active). In contrast, the other two signals must be set to 1.8 V (inactive).3.1.4 Complementary sample signal generation
sample_dac
and \(\overline{\mathtt{sample\_dac}}\). The complementary pass gates are sensitive to asymmetric switching of the control signals: If a state transition of the signals sample_dac
and \(\overline{\mathtt{sample\_dac}}\) are not symmetric, then \(V_{\mathrm{CM}}\) and vdrv
can be shorted, which negatively influences the voltage of \(V_{\mathrm{CM}}\).3.2 Clock generator
3.3 Digital control
3.4 Top-level hardening
m5
is used for the PDN to connect macros to their power rails on m4
. However, a macro inside another macro would be limited to the usage of m3
as the highest layer, and so on.m4
at the lowest hierarchy. According to the documentation, the integration of a macro with MIMCAP layers, as seen in the comparator and \(V_{\mathrm{CM}}\) generator, must be done in the OpenLane core hierarchy. A method has been found to integrate macros at the same hierarchical metal layer as the current PDN generation. The ADC hard-macro IP is hardened as a chip-core using metal layers up to m5
in a way that allows integration into another chip core at metal layer m5
. However, if done correctly, this method violates the documented rules for chip integration, not the process’s design rules. The PDN generator has been found to avoid short circuits and connect macros to the PDN if PORT
layers in the LEF
file at the PDN metal layers m4‑5
are also defined in the FP_PDN_MACRO_HOOKS
configuration of OpenLane, all other nets specified in the LEF
file at the PDN layers must be protected by obstruction OBS
layers. For example, these obstruction layers have been used in the DAC matrix to prevent the generation of m5
structures above the DAC top plate capacitor. The hardened SAR-ADC macro is surrounded by a core ring, which allows power connections of the SAR-ADC to the top-level power network at the edge of the IP block.GDSII
and LEF
file format as input for the custom analog macro cells (DAC, comparator, \(V_{\mathrm{CM}}\) generator, clock generator), and the digital RTL is synthesized, as is shown in Fig. 1. The macros are placed on the top-level macro area by manually specified coordinates at fixed core dimensions. The digital standard cell grid is generated around the placed macros on unused space. The analog macros and the digital standard cell grid are connected to the generated PDN on m4
and m5
. This work uses a vertical m4
and horizontal m5
PDN. For the clock generator, a custom PDN generation Tcl script was used to allow connection from m4
down to m3
, since the power rails of the clock generator have been placed on level m3
. After PDN generation, the clock tree is synthesized, standard cells are placed on the standard cell grid, and routing is performed. After several rounds of optimization, the flow is completed, and the top-level GDS
and LEF
are generated. Since the OpenLane workflow was initially intended for digital workflows, the layout is optimized manually using KLayout for cleaner and wider analog signal routes.
4 Simulation results
ext2spice cthresh 0.1
. The resulting netlist contains 26e3 MOSFETs and 60e3 capacitors. The schematic tool Xschem has been used to build a test environment with disabled averaging, no oversampling, and the fastest clock frequency. The A/D conversion has been simulated using the parallel simulator Xyce at precision settings ABSTOL=1E-15
and RELTOL=1E‑6
. Although Monte Carlo mismatch simulations are possible by using the presented open-source tools, they could not be performed for the proposed SAR-ADC since the design is far too big, leading to a very long simulation time for a reasonable set of data points. However, the proposed SAR-ADC was proven by corner simulations. The plot in Fig. 12 shows a conversion time of \(T_{\mathrm{conv}}=694\,{\text{n}\text{s}}\) which corresponds to a sample rate of \(f_{s}=1.44\,{\text{M}\text{S}/\text{s}}\) at an average power consumption of \(703\,{\upmu\text{W}}\). Table 3 shows the comparable performance of this open-source SAR-ADC to the state-of-the-art, designed with commercial tools. References | ASSCC | ASSCC | CICC | ICECS | GitHub | This work |
---|---|---|---|---|---|---|
[32]’19 | [43]’19 | [4]’19 | [31]’20 | [3]’23 | ||
Process (nm) | 180 | 65 | 65 | 180 | 130 | 130 |
Open-source | no | no | no | no | yes | yes |
Supply (V) | 1.5 | 1.0 | 1.2 | 1.0 | 1.8 | 1.8 |
Resolution (bit) | 12 | 9 | 10 | 14 | 10 | 12 |
OSR | 8 | 8 | 1 | 4 | 1 | 1 |
Sample rate (kHz) | 5120 | 10000 | 4000 | 4.096 | 1560 | 1440 |
Power (\(\upmu\)W) | 180.1 | 130 | 149 | 1.125 | 2100 | 703 |
Area (mm\({}^{2}\)) | 0.192 | 0.072 | 0.24 | 0.349 | 0.149 | 0.175 |
FoM\({}_{W}\) (fJ/step) | 180.7 | 35.9 | 87.7 | 158.2 | 2.12K | 281\({}^{\dagger}\) |
FoM\({}_{S}\) (dB) | 158.1 | 167.8 | 155.6 | 165.2 | 113.5 | 156.6\({}^{\dagger}\) |