12. GALS Clocking and Shared Interconnect for Large-Scale SFQ Systems

A globally asynchronous, locally synchronous clocking scheme for large-scale single-flux quantum systems is described in this chapter. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also presented. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. These approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology—the data packet propagating through the interconnect carries a local clock signal.