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Erschienen in:
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2024 | OriginalPaper | Buchkapitel

13. H-Tree Clock Synthesis in SFQ Circuits

verfasst von : Gleb Krylov, Tahereh Jabbari, Eby G. Friedman

Erschienen in: Single Flux Quantum Integrated Circuit Design

Verlag: Springer International Publishing

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Abstract

Rapid single-flux quantum (RSFQ) technology promises high-performance, energy-efficient supercomputers to achieve exascale computing. An important challenge in VLSI complexity RSFQ circuits is ultra-high-speed clocking and synchronization. A methodology to support the automated design of clock distribution networks for SFQ circuits is the focus of this chapter. Global clock synthesis of SFQ circuits is applied to produce a near-zero skew clock network. An algorithm is presented that produces an SFQ H-tree network with asymmetric leaves to propagate the clock signal to all SFQ gates. A Python-based system with location information for the interconnects, splitters, and leaves is described. The algorithm determines the physical locations and connections within the SFQ clock network and is applicable to automated routing and clock tree synthesis.

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Vorheriges Kapitel GALS Clocking and Shared Interconnect for Large-Scale SFQ Systems
Nächstes Kapitel EDA for Superconductive Electronics
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Metadaten
Titel
H-Tree Clock Synthesis in SFQ Circuits
verfasst von
Gleb Krylov
Tahereh Jabbari
Eby G. Friedman
Copyright-Jahr
2024
Buch
Single Flux Quantum Integrated Circuit Design

Print ISBN: 978-3-031-47474-3

Electronic ISBN: 978-3-031-47475-0

Copyright-Jahr: 2024

DOI
https://doi.org/10.1007/978-3-031-47475-0_13

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